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--- aira:start [2022/06/21 11:49] – [Schedule] sbk
+++ aira:start [2022/06/23 13:25] – [Schedule] sbk
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 ===== Schedule=====
   * **[DOCTORAL TRACK] 2022.06.23** : Bartosz Soból [[#20220623|AI inference acceleration on FPGA]]
-    * Meeting link: [[|MS Teams]]
+    * Meeting link: [[https://teams.microsoft.com/l/meetup-join/19%3aJF1L0935A7eV6s8R9brG5MMYONrqy4XmxPSYLeRMCGM1%40thread.tacv2/1655812380995?context=%7b%22Tid%22%3a%22eb0e26eb-bfbe-47d2-9e90-ebd2426dbceb%22%2c%22Oid%22%3a%22c96e4eee-96f3-4b0f-88ef-fe65310f5f55%22%7d|MS Teams]]
     * Recording: [[|View]] (if you are not UJ empoyee, ask [[mailto:szymon.bobek@uj.edu.pl|Szymon Bobek]] for access)
     * Presentation slides: TBA
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   * **2021.10.14** [[http://acai2021.org|Challenges and Opportunities for human-centred AI]]: A dialog between Yoshua Bengio (Turing Award) and Ben Shneiderman, moderated by Virginia Dignum.
     * Meeting link: **[[https://hertie-school-org.zoom.us/j/94694805550?pwd=eTZXbHNMdngvajUwanZpZDBTTDRqUT09|Zoom link]]**
+==== 2022-06-23 ====
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+**Speaker**: Bartosz Soból,  PhD Candidate @ Jagiellonian University
+**Title**: AI inference acceleration on FPGA
+**Abstract**:
+Artificial intelligence and neural networks are constantly applied in all sorts of tasks involving data processing. Emerging models are deployed on different kinds of computing platforms: from edge computing, through the cloud, and ending with HPC.
+Modern FPGA-based accelerators and SoCs aim to fulfill different needs in all of the above levels such as high throughput, low latency, high energy efficiency, and flexibility.
+New software stacks are developed to expose high-level interfaces for preparing, optimizing, and deploying existing or custom, implemented in standard machine learning frameworks such as PyTorch or TensorFlow, models on FPGA devices.
+In this talk, I will present modern solutions for accelerating the inference of neural network models on FPGAs as well as examples of usage done by us at the JU and from others.
+**Biograms**:
+**Bartosz Soból** is a first-year Ph.D. student in Technical Computer Science at Jagiellonian University. He holds a BSc in Computer Mathematics and MSc in Computer Science from Jagiellonian University.
+Currently, he is a member of PANDA (FAIR, GSI) collaboration where he conducts research on particle tracking algorithms and heterogeneous online processing of experimental data. His professional interests include high-performance computing, software optimization for heterogeneous systems, and CPU-GPU-FPGA interoperability.
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